On January 19, Capital Microelectronics issued the first FPGA chip CME-C1 at its press conference.

CME-C1 is the first FPGA chip in the “cloud” series products for the FPGA market. It uses the TSMC 40nm CMOS technology, and its logical volume varies from 30K to 200K.

The “cloud” series uses the brand new LUT 6 structure and 32-access full clock network, and the operation speed can reach 700MHz. To cater to the high-speed big volume market, CME-C1 also integrates the Serdes interface which has the biggest volume of 6.5G, DDR2/3 controller of hardcore, hardcore PCle interface, and 36×18 DSP processor.

According to Wang Haili, market president of Capital Microelectronics, CME-C1 is leading in key technological standards in China, and fills the gap in the FPGA Chinese market. CME-C1 is also a national level innovative project in nuclear, high-end, basic technologies in the twelfth five-year plan. After years of research and technological experiments, CME-C1 was successfully created by the end of 2015.

The chip is expected to go into use in June, 2016. Another product of “cloud” series, CME-C6, will be launched in July.